1. Field of the Invention
The present application relates to a method of fabricating nonvolatile, electrically writable and erasable semiconductor memory devices having a floating gate electrode.
2. Description of the Related Art
Among nonvolatile semiconductor memories that are electrically writable and erasable (EEPROMs), the popularity of flash EEPROMs, also known as flash memories, has increased in recent years. In conventional EEPROMs, erasing is generally performed bit by bit, while in flash memories erasing is performed block by block. Although block-by-block erasing makes flash memory devices more difficult to use as compared to conventional EEPROMs, the simple structure of flash memory devices in which one bit of data is stored in a single cell and data is erased in blocks allows flash memory devices to be highly integrated. As a result, the density of flash memory devices is similar to or greater than the that of dynamic random access memory devices (DRAMs). This high integration density makes flash memory devices desirable for use as next generation read only memory devices.
With the increased interest in flash memory devices, various structures of flash memories have been proposed. One such flash memory device is disclosed in U.S. Pat. No. 5,280,446. FIGS. 21 to 23 illustrate such a flash memory device. FIG. 21 is a plan view of this flash memory device, FIG. 22 is a cross-sectional view of the device of FIG. 21 taken along line S-S', and FIG. 23 is a cross-sectional view of FIG. 21 taken along line C-C'. In this flash memory device, each memory cell has a channel region L, including two subchannel regions L1 and L2, that is formed on a substrate 100 or in a well between a source line 8 and a drain line 7. On the subchannel region L2 located adjacent the source line, a select gate electrode 9a is formed on a gate dielectric layer 10. On the subchannel region L1 located adjacent the drain line, a floating gate electrode 4 is formed on a tunnel oxide film 3.
Each memory cell is isolated by a device isolation field oxide layer (LOCOS) 2 formed on the substrate 100. A control gate is formed on the floating gate 4. The control gate 6 includes a control gate electrode 6a and an insulating layer 6b formed on the control gate electrode. The control gate 6 is made up of a line-shaped polysilicon layer disposed on the floating gate 4 via an inter-poly dielectric layer 5. The control gate 6 extends along the channel width (W). The floating gate 4 and the control gate 6 form a first multilayer region (hereinafter referred to as a stacked gate structure). A select gate 9 is formed on the stacked gate structure and also on a second region on the substrate adjacent the stacked gate. This second region is also referred to as a split gate region. The select gate is formed on the stacked gate structure and the split gate region via insulating films 6b and 10, respectively. The select gate line 9 includes a select gate electrode 9a and an insulating layer 9b formed thereon.
The source line 8 and the drain line 7 are each formed of a substrate diffusion region extending parallel to the control gate 6. The source line 8 is in an offset position relative to the control gate 6. As indicated above, the channel region L between the source line 8 and the drain line 7 consists of two subregions L1 and L2 corresponding to the stacked gate region and the split gate region, respectively. The subregion L1 is also referred to as a drain side channel region and the subregion L2 is also referred to as a source side channel region.
In FIGS. 21-23, reference numeral 1 denotes an active substrate region, and reference numeral 50 denotes a contact hole. With the above structure, channel hot electrons are injected into the floating gate 4 from the region between the stacked gate structure (the region where the floating gate exists) and the split gate region. The above injection technique is known as source side injection (SSI) and allows a high electron injection efficiency.
With the memory elements (or cells) arranged in an array or matrix, any one memory element can be selected by designating a control gate 6 and a select gate 9 thereby designating an intersection. Further, two neighboring memory elements in the array which are directly adjacent to each other via a diffusion region (source or drain) may share the same source or drain. This allows a reduction in the cell area and thus an increase in the integration density.
For the device shown in FIGS. 21-24, the substrate diffusion layers are formed as follows. A resist pattern 30 is formed over, for example, a portion of the stacked gate structures and subregions (e.g., subregion L2) of the channel region L by means of photolithography processing. Then impurity ions (such as arsenic ions or phosphorus ions) are implanted into the substrate using the resist pattern 30 as a mask. In the above process of forming the diffusion layer, the implantation for the drain line 7 is preformed in a self-alignment fashion, while the position of the source line is defined by the resist mask 30.
In the above technique, since formation of the source line 8 involves using the resist film 30 as a mask and patterning by means of the photolithography technology, the uniformity of the channel length of the select gate 9 of the flash memory device is limited by the alignment accuracy of the photolithography process. Variations in the channel length can cause an increase in leakage current over the entire memory array. Channel length variations can also cause variations in the threshold voltage and the "on" voltage of a select transistor and the "on" current of memory cell. These variations in the memory characteristics can lead to memory cell failure, and limit the minimum size of conventional flash memory devices.
One attempt to overcome this drawback and achieve further reductions in the memory cell size, was to use a self-alignment technique in terms of the split gate length. Japanese Patent Application No. 8-52915 discusses such a split gate length self-alignment technique. This technique is characterized in that a first side film is formed on the side of the multilayer structure consisting of the floating gate electrode and the control gate electrode, then impurity ions are implanted into a region intended to become a source line in a self-alignment fashion using the first side wall film as a mask to form the source line. A second side wall film having a thickness (measured in a lateral direction in the structure) that is smaller than the thickness of the first side wall film is then formed. The second side wall is used as an insulating layer between the stacked gate and the select gate.
However, in the technique discussed in the Japanese application, a large number of steps are required to fabricate such a memory device. Further, the techniques used to fabricate such memory devices are complex. As a result, the fabrication processes for making these memories is time consuming and costly.